Welcome to My Research page!!

Current Reseach Focus: Currently I am working on high performance VLSI architecture for IP Lookup, packet classification and multi-match packet classification, which is typically the core function in the switches/routers, firewalls/routers and Network Intrusion Detection System (NIDS) respectively. The goal is to design high performance basic network functions and improve the performance of IP lookup, packet classification and Multi-match packet classification by using hardware design, algorithms and architectures. The designed modules will be used and will incrementally build the network systems like routers, firewall and NIDs using ASICs and FPGA based designs.

High Performance VLSI Architectures for Digital Signal Processing: The core objective of this work is to build a high performance VLSI architectures for discrete orthogonal transforms, which will deliver high speed characteristics, consumes lesser area on the chip and power efficient. Currently I am focusing on improving the basic transforms that are used in the image and video processing. The proposed design can be deployed in the mobile phones to save battary life. The proposed designs will be available as an IP Cores for the research community for further enhancement of the functionality of the given block.

Software aspects of VLSI Design: Objective is design and develop an efficient algorithms that designs a larger and scalable hardware block, which will be faster, area and power efficient. A software tool will be developed using the proposed core algorithm to generate the larger hardware blocks. The developed software tool will be available as an opensoure for the researchers to further enhance the performance of the hardware block or mega function.

High Performance Packet Processing Architectures and Algorithms: The objective of this work is to focus on the design and development of an high performance VLSI architectures and Algorithms for the packet processing in network systems. The proposed architectures will be implemented and will be available as an hardware IPs for researchers for further enhancement in the performance.