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Feature Extraction Engine for Speech Recognition System with 16KHz Sampling Frequency
M Dhayalakumar, Skanda Deepsita, & Noor Mahammad Sk

Sponsored by Ministry of Electronics and Information Technology, Govt. of India

  1. Objectives of the Research:

    2. The following are the major objectives of the work:

    • Design a feature extraction engine ofspeech recognition system.
    • On-the-fly speech to text conversion rather using the cloud based approaches.
    • Proposed design is independent of language
    • Energy efficient design
    • Reduce the delay of processing

  2. Deliverables of the research:

    3. The following are the key deliverables of this research:

    1. Efficient MAC (Multiply Accumulate).
    2. Design of 256 point Fast Fourier Transform hardware.
    3. Design of 16 point Fast Fourier Transform hardware.
    4. Design of 8 point Fast Fourier Transform hardware.
    5. Low cost Square root circuit.
    6. Efficient Memory optimized Mel Filter Bank Computation hardware.
    7. High Speed Mel Frequency Filtering of speech frame.
    8. Efficient Extraction of Cepstral Coefficients from the Mel Energies of Input Speech.
    9. Feature extraction engine hardware for 8KHz Sampling frequency.
    10. Design of 512 point Fast Fourier Transform hardware.
    11. Design of 64 point Fast Fourier Transform hardware.
    12. Feature extraction engine hardware for 16KHz Sampling frequency.
    13. Simulation of 8 KHz and 16 KHz Sampling frequency FEE model is completed.

  3. Technical Specifications:

    4. Parameters Values Definition
    Sampling Rate (F_s) 16 KHz >= 2F_N
    Input Frequency (F_N) KHz 300Hz to 3.3 KHz Voice Signal Range
    Number of Bits per Sample (n) 16 ADC Resolution
    Frame Period (T_f) 25 ms Number of Samples per Frame
    Overlap Period (T_OL) 15 ms Number of Overlap Between Frame
    Number of Frames per Second (N_F) 100(98+2*) Throughput
    Number of Samples per Frame (N_s) 400 (F_s. T_f)
    FFT Size (N) 512 Point >= N_s
    Number of Mel Filters (M) 20 F_s --> (20 to 40)
    Number of Cepstra (N_L) 12 per frame MFCC Order
    MFCC Order (DCT Coeff) 12 = N_L
    Non Zero Coefficients (Mel Co-eff) 477 N_c
    Number of Clock cycle per frame 160

  4. Overview of the Research Work:

  5. Detailed Implementation Details:

  6. Detailed Simulation Details:
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